connectors 07/17/09 preliminary specifications and applications information 10m package pcb components are shown for reference only. actual product may differ from that shown. page 1 of 3. package configuration the erg 10M123920F ( 10m class 10m class 10m class 10m class 10m class ) low profile dc to ac inverter is specifically designed to power the following display module(s) to a moderate brightness level from a +12 volt dc power supply: ? sharp lq085y3dg06 this low profile inverter features: 9 less than 10 mm in height 9 lcd module specific 9 display compatible output connector 9 firm specifications 9 application information 9 designed, manufactured and supported in the usa 9 custom input and output voltages 9 flexible system interface pcb components are shown for reference only. actual product may differ from that shown. j1-1,2 +vin j1-3,4 gnd j1-5 enable j1-6,7,8 n/c j2-1 acout j2-2 acreturn input connector molex 53261-0871 output connector jst sm02(8.0)b-bhs-1n-tb mass: 22 grams 1 3.060 [77,72] .120 [3,05] dia.(2x) 4.32 [109,7] .54 [13,7] .16 [4,1] .97 [24,6] input 1 .525 [13,34] output 10M123920F 10m class 10m class 10m class 10m class 10m class single lamp dc to ac inverter
page 2 of 3. made in usa specifications subject to change without notice. (note 1) surface temperature must not exceed 80 degrees c; thermal management actions may be required. (note 2) input current in excess of maximum may indicate a load/inverter mismatch condition, which can result in reduced reliability. please contact erg technical support. (note 3) provided data is not tested but guaranteed by design. (note 4) required user enable/disable interface circuit is shown on page 3. application notes: 1) the minimum distance from high voltage areas of the inverter to any conductive material should be .12 inches per kilovolt of starting voltage. 2) mounting hardware to be non-conductive. 3) open framed inverters should not be used in applications at altitudes over 10,000 feet. 4) acreturn should be left floating, not grounded. 5) contact erg for possible exceptions. s g n i t a r m u m i x a m e t u l o s b a g n i t a rl o b m y se u l a vs t i n u e g n a r e g a t l o v t u p n i v n i 2 . 3 1 + o t 3 . 0 -c d v e r u t a r e p m e t e g a r o t s t g t s 5 8 + o t 0 4 - o c s c i t s i r e t c a r a h c g n i t a r e p o . s e t u n i m 5 f o p u - m r a w p m a l d n a y a l p s i d d e c n e r e f e r e h t g n i t a l u m i s d a o l a h t i w 5 2 = a t d n a c d s t l o v 0 0 . 2 1 = n i v d e t o n e s i w r e h t o s s e l n u o c c i t s i r e t c a r a h cl o b m y sn i mp y tx a ms t i n u e g a t l o v t u p n i v n i 8 . 0 1 +0 . 2 1 +6 . 2 1 +c d v e c a f r u s t n e n o p m o c e r u t a r e p m e t ) 1 e t o n ( t s 0 2 --0 8 + o c t n e r r u c t u p n i ) 2 e t o n ( i n i -7 4 . 04 5 . 0c d a y c n e u q e r f g n i t a r e p o f o 4 29 24 3z h k e g a t l o v t u p t u o m u m i n i m ) 3 e t o n ( v t u o ) n i m ( 0 0 3 2--s m r v y c n e i c i f f e h h h h h -0 9-% ) p m a l r e p ( t n e r r u c t u p t u o i t u o -3 . 5- s m r a m e g a t l o v t u p t u o v t u o -0 6 9- s m r v t n e r r u c t u p n i n i p e l b a n e t n e m e r i u q e r ) 4 e t o n ( i e l b a n e -5 . 4- c d a m e g a t l o v t u p n i n i p e l b a n e t n e m e r i u q e r ) 4 e t o n ( v e l b a n e f f o g n i t a o l f r o 0 n o 0 . 2 1 n o n i v c d v 10M123920F
page 3 of 3. u l ? r e g i s t e r e d f i r m r e g i s t e r e d f i r m e n d i c o t t r e s e a r c h g r o u p , i n c . i s o 9 0 0 1 a 3 3 1 3 endicott research group, inc. (erg) reserves the right to make changes in circuit design and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by erg is believed to be accurate and reliable. however, no responsibility is assumed by erg for its use. 10M123920F +vin 1,2 3,4 5 5% - 100% (2) v pwm pwm frequency 100-300 hz should be selected to be compatible with lcd and display driver. (1) 0 r1 r2 2n3906 2n3904 10k +vin required user enable/disable interface circuit (1) low esr type input by-pass capacitor (22 uf - 100 uf) may be required to reduce reflected ripple. (2) v pwm from 2.4v to less than or equal to +vin. (3) full brightness without pwm control requires that pin 5 be tied to +vin. pin 5 must be at 0v to turn off. (4) duty cycle 5% - 100%. n i v1 r2 r v 5k 3 . 3k 5 . 1 v 8k 3 . 3k 8 . 1 v 2 1k 3 . 3k 2 . 2 v 4 2k 0 . 0 1k 2 . 8 pwm dimming (4) (3) gnd circuit or equivalent required for proper inverter turnoff.
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